The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs. As this progression takes place, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as fin-like field effect transistor (FinFET) device. A typical FinFET device is fabricated with a thin “fin” (or fin-like structure) extending from a substrate. The fin usually includes silicon and forms the body of the transistor device. The channel of the transistor is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin. This type of gate allows greater control of the channel. Other advantages of FinFET devices include reduced short channel effect and higher current flow.
Fabrication of FinFET devices usually requires a computed-aided design (CAD) layer that defines the boundary of FinFET devices. This is done so that the FinFET devices can be fabricated in an area of a chip separate from traditional semiconductor devices (referred to as planar devices). When a semiconductor foundry receives a design layout from a customer, this FinFET boundary is usually not defined, since a customer may have implemented the layout of its chip using only planar devices. Consequently, the foundry may need to convert portions of the chip from a planar layout to a FinFET layout. However, this conversion process may violate a number of FinFET design rules.
Therefore, while existing methods of fabricating FinFET devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.